Telecommunication contractor switching centers, such as used in a private branch or automatic exchange, use a variety of architectures to handle contacts. In one configuration depicted in FIG. 1 and sold by Lucent Technologies, Inc., under the tradename Definity™, the switching center includes a controlling architecture 10 that includes a processor 14, a memory 18, and a packet control driver 22; a packet interface 26 that includes a processor 30 and memory 34; dual port RAM 36 that includes tables 38 (e.g., link address table, link control table, link data table, link status table, etc.), queues 42, and variables such as counters 46 and interrupts 50; one or more memory (ISDN) boards 54 (which are attached to the packet interface by way of packet bus 58); and telephones 62(which are attached to the boards 54 by link access procedure for the D-channel (LAPD) links). A “link” refers to any kind of communication path between two computational components. The packet interface 26 and dual port RAM 36 are typically located on a common board 66 while the controlling architecture 10 is located on a separate board in the same enclosure.
The packet control driver and packet interface communicate with one another by means of the dual port RAM. As will be appreciated, the packet control driver 22 includes software that controls the packet interface 26 and provides interfaces to application software in the architecture 10 for accessing the packet interface's capabilities. The packet interface 26 terminates LAPD and includes firmware that interfaces to the packet bus 58 through various known devices. The controlling architecture 10 and packet interface 26 each access the dual port RAM 36 via memory buses 68a,b. In this manner, both the packet control driver 22 and packet interface 26 access the same memory locations when they are communicating with one another. To provide direct control of the packet interface, one or more interrupt lines 70 connect the architecture 10 directly to the packet interface 26.
The architecture has certain limitations. For example, the distance of separation between the architecture 10 and the packet interface 26 must be relatively small. The close proximity of the two components results from the requirement that the architecture 10 access the dual port RAM 36 via a memory bus 68a and from the flow control technique employed by the architecture 10 and packet interface 26. The architecture 10 and packet interface 26 employ a simple, escalating XON/XOFF flow control technique that is not optimal in an environment where the two entities are a variable distance apart and each message could have a variable (>0) amount of delay. The separation distance limitation restricts the versatility of the system. By way of illustration, for the controlling architecture 10 to control multiple port networks (each port network including a packet interface 26, one or memory boards 54, and attached telephones 62) a first Expansion Interface (EI) board is connected to the packet bus 58 and to a second EI board, and the second EI board is connected to a packet bus 58 of another port network (not shown). As can be seen from the illustration, a large number of boards are employed to increase contact center capacity which increases the cost of the system, and all port network messages are routed inefficiently through a single packet bus 58 of a selected port network.